I am Zesong Jiang, a Ph.D. student in Electrical, Computer and Energy Engineering at Arizona State University, advised by Prof. Jeff Zhang and working closely with Cheng Tan. I received my M.S. from the University of Science and Technology of China (USTC) in 2025 and my B.S. from Jilin University in 2022.
My research focuses on AI for Chip Design and Computer Architecture, particularly LLM-based Design Automation, Reconfigurable Accelerators (CGRA), and Hardware/Software Co-Design. I am currently a Research Intern at IBM Silicon Valley Lab.
I welcome research discussions and collaborations. You can reach me at zjian137@asu.edu.
🔥 News
- [May. 2026] [Position] Joined IBM Silicon Valley Lab as a Research Intern.
- [May. 2026] [Publication] Our work “MACO: A Multi-Agent LLM Framework for Automated CGRA Hardware/Software Co-Design” was accepted to ICLAD 2026.
- [May. 2026] [Publication] Our work “CAPO: Certification-Guided Agentic Workflow for Physical Design Parameter Optimization” was accepted to GLSVLSI 2026.
- [Mar. 2026] [Invited Talk] Presented MACO at the NSF Workshop on Agents for Chip Design Automation.
- [Aug. 2025] [Education] Began my Ph.D. at Arizona State University.
- [Jun. 2025] [Honor] Named an Outstanding Graduate of Anhui Province upon graduating from USTC.
📝 Publications
MACO: A Multi-Agent LLM Framework for Automated CGRA Hardware/Software Co-Design ICLAD 2026 Automates CGRA hardware/software co-design through four collaborative stages: design generation, error correction, best-design selection, and evaluation with feedback. Evaluation reports 25.9% lower power, 20.0% higher performance, and 5× faster design-space search, with final designs validated through a complete 7 nm ASIC flow. Paper
CAPO: Certification-Guided Agentic Workflow for Physical Design Parameter Optimization GLSVLSI 2026 Formulates physical-design optimization as certified trajectory control, combining structured flow-state abstraction, bottleneck-aware planning, and transition certification to reject harmful actions and support recovery across coupled design stages. Paper
IICPilot: An Intelligent Integrated Circuit Backend Design Framework Using Open EDA Preprint 2024 Automates backend-design script generation, EDA-tool execution, parameter exploration, container resource allocation, and exception handling through specialized agents and a unified interface for OpenROAD and iEDA. Paper
Break the Cold Barrier: An In-Depth Study on FPGA Performance and Design Optimization at Cryogenic Temperature Integrated Circuits and Systems 2024 Characterizes FPGA behavior at cryogenic temperature and uses CryoFPGA-Pilot to explore a 500-point architecture space for low-delay and low-power designs. Paper
SigDLA: A Deep Learning Accelerator Extension for Signal Processing Preprint 2024 Extends a conventional deep-learning accelerator with programmable data shuffling and a reconfigurable compute array, converting irregular signal-processing patterns into regular operations while preserving deep-learning support. Paper
A Low-Field Magnetic Resonance Signal Transmission and Reception Processing Platform ICICSP 2024 Implements low-field MRI transmission and reception on an FPGA: direct digital synthesis generates adjustable RF pulses, while digital downconversion and CIC/FIR filters recover baseband signals. Paper
A Biodegradable Piezoelectric Scaffold Promotes Spinal Cord Injury Nerve Regeneration Nano Energy 2024 Develops a biodegradable PLLA/KNN@PDA piezoelectric scaffold that provides structural guidance and sustained electrical stimulation, promoting neural growth and functional recovery in a rat spinal-cord injury model. Paper
💻 Experience
IBM Silicon Valley Lab, San Jose, CA, USA May 2026 – Present Research Intern — building a reliable agentic workflow for long-horizon physical design, optimizing chip PPA and reducing manual design effort.
Arizona State University, Tempe, AZ, USA Aug 2025 – Present Graduate Research Assistant — LLM for Chip Design; Reconfigurable Accelerator; HW/SW Co-Design.
🎤 Talks
- 2026.03: MACO: A Multi-Agent Framework for LLM-Driven Hardware/Software Co-Design, NSF Workshop on Agents for Chip Design Automation.
🎖 Honors and Awards
- 2026: Student Travel Award, NSF Agents4Chip.
- 2025: Outstanding Graduate of Anhui Province (12 out of 305).
- 2025: Outstanding Graduate of the University of Science and Technology of China.
- 2022 – 2024: Graduate Scholarship — First Prize, University of Science and Technology of China.
- 2018 – 2022: Undergraduate Scholarship — First Prize, Jilin University.
📖 Education
- 2025.08 - Present, Ph.D. Student, Electrical, Computer and Energy Engineering, Arizona State University. Advisor: Prof. Jeff Zhang.
- 2022.09 - 2025.06, M.S., Electrical & Computer Engineering, University of Science and Technology of China. Advisor: Prof. Bensheng Qiu. (GPA 3.87/4.3, Rank 1/27)
- 2018.09 - 2022.06, B.S., Electrical & Computer Engineering, Jilin University. (GPA 3.76/4.0, Rank 21/335)
🛠 Skills
- Programming: Verilog, C/C++, Python
- EDA Tools: Synopsys Design Compiler, OpenROAD, Yosys, VTR, COFFE, Vivado, Quartus, Hspice, Verilator, Altium Designer
- Tools: Git, Bash, MATLAB, LaTeX, VS Code





